This disclosure relates to integrated circuit devices, and more specifically, to a method and structure to create advanced metal conductor structures in semiconductor devices.
In many mixed signal or high frequency RF applications in integrated circuits, high performance, high speed capacitors are required. A metal insulator metal (MIM) capacitor is used commonly in high performance applications in CMOS and other semiconductor technologies. Such a capacitor has a sandwich structure and can be considered analogous to a parallel plate capacitor. The capacitor top metal (CTM) is separated from the capacitor bottom metal (CBM) by a thin insulating layer. Both of the two parallel metal plates are conventionally made from Al or AlCu alloys. These metals are patterned and etched needing several photolithography masking steps. The thin insulating dielectric layer is usually made from silicon oxide or silicon nitride deposited by chemical vapor deposition (CVD) or other deposition processes.
As the dimensions of modern integrated circuitry in semiconductor chips continues to become smaller, conventional lithography is increasingly challenged and expensive to make smaller and smaller structures. A conventional process for creating an MIM capacitor is expensive as it requires at least three additional masks (alignment mask, top electrode mask, bottom mask) to fabricate the capacitor, as well as additional including lithography and RIE processes. Further, as the dimensions of the capacitor decrease, there is a scaling challenge in maintaining the uniformity of the dielectric thickness throughout the MIM capacitor as the dielectric thickness is decreased with the rest of the device.
The present disclosure presents an advanced MIM capacitor to alleviate this problem.